Some of the most time-consuming tasks in PCB design are placing parts on the board and routing traces. Designers who complete these tasks efficiently can make a more positive and direct impact on design quality and development time than designers who do not. PADS offers outstanding placement and routing capabilities that reduce the design cycle and improve product quality.
This Case Study explores how they installed energy management software and intelligent rack PDUs with outlet-level power monitoring to add remote energy management, power monitoring of individual devices, environmental monitoring, and sophisticated and accurate power usage reports and analytics.
Virtualization presents a tremendous opportunity for IT organizations. Yet deployment involves major process and management complexities.
This white paper outlines best-practice methodologies that help you tackle challenges brought on by virtualization. We also suggest key questions to ask when evaluating a consolidated management solution.
"As the number of enhancements to various Hardware Description Languages (HDLs) has increased over the past year, so too has the complexity of determining which language is best for a particular design. Many designers and organizations are contemplating whether they should switch from one HDL to another.
This paper compares the technical characteristics of three, general-purpose HDLs.
A powerful signal integrity analysis tool must be flexibility, easy to use and integrated into an existing EDA framework and design flow. In addition, it is important for the tool to be accurate enough. This report reviews a validation study for the Mentor Graphics HyperLynx 8.0 PI tool to establish confidence in using it for power integrity analysis.
For advanced signaling over high-loss channels, designs today are using equalization and several new measurement methods to evaluate the performance of the link. Both simulation and measurement tools support equalization and the new measurement methods, but correlation of results throughout the design flow is unclear. In this paper a high performance equalizing serial data link is measured and the performance is compared to that predicted by simulation. Then, the differences between simulation and measurements are discussed as well as methods to correlate the two.
High Density Interconnect (HDI) is being used more often to meet the growing need for more complex designs in smaller form factors. Beyond some of the more obvious electrical effects of using smaller vias, there is also an impact to the power integrity of a board using HDI. This includes different effects of mounted inductances of decoupling capacitors, changes in plane performance due to reduction in perforation from chip pinouts, and the inherent plane-capacitance changes from using dielectrics of various thicknesses. This paper will examine and quantify these effects, using numerous design examples, including a large conventional through-hole design board that was reduced using HDI.
The success of any consumer electronic device depends to a large extent on the appeal of the user interface (UI) and how easy the device is to use. Studies show that good cosmetic design can encourage users to explore the full range of features and often engenders the perception that a product is easier to use. So if the benefits of a great looking, easy-to-use UI are so clear, why are so many products still falling short of customer expectations? The solution lies in taking a fresh new approach a consumer electronic device UI plays. By identifying common UI functionality and implementing it in a reusable and customizable way, we can make it far easier for embedded engineers to deliver visually engaging and easy-to-use consumer electronic products.
Moving to C++ presents opportunities for higher programmer productivity. The requirements of embedded systems, however, demand that the adoption of C++ be carefully measured for the performance impact of run-time costs present in C++, but not in C. This talk suggests strategies for developers who are starting their acquaintance with C++.
This white paper explores the challenges of increasing computing power in resource-constrained physical spaces and data centers experiencing high growth. We also explore how intelligent rack PDUs can meet these challenges and address critical uptime and capacity planning issues.
Voice Over IP (VoIP) deployments can cause unexpected or unplanned power and cooling
requirements in wiring closets and wiring rooms. Most wiring closets do not have
uninterruptible power available, and they do not provide the ventilation or cooling required to prevent equipment overheating. Understanding the unique cooling and powering needs of VoIP equipment allows planning for a successful and cost effective VoIP deployment. This paper explains how to plan for VoIP power and cooling needs, and describes simple, fast, reliable, and cost effective strategies for upgrading old facilities and building new facilities.